1. Field of the Invention
The present invention relates to a twin well CMOS (complimentary metal oxide semiconductor) device, and a fabrication method therefor. More particularly, the present invention relates to a twin well CMOS device and fabrication method therefor which are less susceptible to lateral diffusion of a well caused by misalignment in lithography.
2. Discussion of Conventional Art
FIG. 1 is a cross-sectional view of a related art semiconductor device.
The related art semiconductor device, e.g., a CMOS inverter circuit, has P well 22b and N well 21 which are formed in a P-type semiconductor substrate 11. An insulating oxide layer 13 is formed to define the active and isolation regions of the device. Heavily doped P-type regions 27 and 28 are formed in the N well 21 by using a first gate 37 overlying a gate insulating layer 23 as a mask. A heavily doped N-type region of N-well contact 30 is then formed at a predetermined portion in the N well 21. The heavily doped P-type regions 27 and 28 become the drain and source regions of P-channel FET, respectively. Heavily doped N-type regions 25 and 26 are formed in the P well 22b by using a second gate 38 overlying the gate insulating layer 23 as a mask. A heavily doped P-type region of P-well contact 29 is then formed at a predetermined portion in the P well 22b. The heavily doped N-type regions 25 and 26 become the source and drain regions of N-channel FET, respectively. A heavily doped P-type buried layer 22a surrounds the N well 21 completely.
In the CMOS inverter circuit 39 having the above-described structure, the P-well contact region 29 and the source region 25 of N-channel FET are connected to a ground line VSS, while the source region 28 of P channel FET and the N-well contact region 30 are connected to a power source VDD. The first and second gates 37 and 38 are connected to an input line VIN, and the drains 26 and 27 of N channel and P channel FETs are connected to an output line VOUT.
In operation, a signal applied to line VIN at a high logic voltage level will cause the N channel FET to turn on. At the same time, it turns the P channel FET off, such that substantially no current flows between the drain and source regions 27 and 28 of P channel FET.
The output line VOUT connected to the drain regions 26 and 27 is therefore pulled to the lower supply voltage VSS through the N channel FET. The CMOS inverter circuit 39 therefore effectively inverts an input high logic voltage level to an output low logic voltage level. P+ layer 22a is heavily doped with p type impurities that works as a p+ guard ring around an NMOS transistor to separate NMOS and PMOS transistors to be fabricated in the corresponding conductive type wells, thereby minimizing the possibility of latch-up.
FIGS. 2A to 2D show cross-sectional views of a semiconductor device of the related art during its fabrication in which six ion-implantations are carried out by controlling the parameters of the ion accelerator in the ion injection apparatus.
Referring to FIG. 2A, an insulating layer 13 for device isolation is formed on a p-type semiconductor substrate 11 by local oxidation of silicon (LOCOS) to define active regions of a device. A first photoresist 111 is formed on the substrate 11, except the region where an N well is formed by ion implantation where a photoresist 111 is formed with a thickness of 2.0 xcexcm. A first ion implantation (101) is carried out on the exposed substrate 11 with P ions having implantation energy of 1.0 MeV, thereby forming a lower layer 101 of a retrograde N well. Then, a second ion implantation (102) is carried out on the exposed substrate 11 with P ions having implantation energy of 450 KeV, thereby forming an upper layer 102 of a retrograde N well. A third ion implantation (103) is carried out on the exposed substrate 11 with P ions having an implantation energy of 60 KeV, thereby forming a threshold voltage controlling layer 103 of a retrograde N well at the top portion of the substrate 11.
Referring to FIG. 2B, with the same photoresist 111 exposing the N well area only, a fourth ion implantation (141) is carried out on the entire substrate 11 with B ions having an implantation energy of 2.0 MeV which is high enough to penetrate through the first photoresist 111 into the substrate of P well forming area, thereby forming an upper layer 141 of a retrograde P well and a guard ring layer 140 at the lowest part of the N well forming area in the substrate 11. In this case, the guard ring layer 140 helps to isolate the N well from the substrate and the neighboring P well completely after diffusion of the B impurities.
Referring to FIG. 2C, after the first photoresist has been removed from the substrate 11, a second photoresist 112 is formed on the substrate 11 except the region where a P well will be formed. A fifth ion implantation (142) is carried out on the exposed substrate 11 with B ions having an implantation energy of 1.25 MeV, thereby forming a lower layer 142 of the retrograde P well at the bottom portion of the substrate 11. Finally, a sixth ion implantation (143) is carried out on the exposed substrate 11 with P ions having an implantation energy of 750 KeV, thereby forming a threshold voltage controlling layer 143 of the retrograde P well at the top portion of the substrate 11.
Referring to FIG. 2D, annealing is carried out on the entire substrate including the above ion-implanted layers, thereby forming a P well 15 and an N well 16 as well as a bottom layer 17 of p type under the N well 16.
The related art clustered ion implantation experiences some problems since it is performed at an acceleration voltage having a magnitude measured in MeV. For instance, ion implantations at such a high acceleration voltage may cause point defects with high density, which may lead to an increase in the junction leakage current. Misalignment in lithography causes the punch-through voltage of n+/N-well and p+/P-well located at a well edge to be lowered.
In addition, when performing ion implantations at a high acceleration voltage in MeV, the thickness of photoresist may be varied by erosion, causing non-uniformity of the photoresist, such that the profile of ion implantation deviates from the set target, thereby producing variations in implant profiles.
The present invention is directed to system that substantially obviates one or more of the problems experienced due to the above and other limitations and disadvantages of the related art.
An object of the present invention is to provide a semiconductor device and fabrication method therefor which reduce the lateral diffusion of wells at a well edge.
Another object of the present invention is to provide a semiconductor device and fabrication method therefor which avoid the effective formation of a parasitic circuit around a CMOS, which is known commonly as latch-up.
Other and further objects, features and advantages of the present invention will be set forth in the description that follows, and in part will become apparent from the detailed description, or may be learned by practice of the invention.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes a semiconductor device having a semiconductor substrate having a first conductivity type; a first well having a second conductivity type formed in a first region in a major surface of the semiconductor substrate by serial ion implantations; and a second well having the first conductivity type formed in a second region in the major surface of the semiconductor substrate by serial ion implantations.
To achieve the second object of the present invention, a method of fabricating a semiconductor device includes: selectively forming an insulating oxide layer in a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate has first and second regions; forming impurity layers having a second conductivity type in the first and second regions of the semiconductor substrate; forming a first mask layer in the second region of the semiconductor substrate; forming impurity layers having the second conductivity type in the first region of the semiconductor substrate by performing serial ion implantations with different doses of dopants at different acceleration energies; forming a second mask layer in the first region of the semiconductor substrate; and forming impurity layers having the first conductivity type in the second region of the semiconductor substrate by performing serial ion implantations with different doses of dopants at different acceleration energies.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. Thus, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of example only. Various changes and modifications that are within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. In fact, other objects, features and characteristics of the present invention; methods, operation, and functions of the related elements of the structure; combinations of parts; and economies of manufacture will surely become apparent from the following detailed description of the preferred embodiments and accompanying drawings, all of which form a part of this specification, wherein like reference numerals designate corresponding parts in various figures.